Hook
The race wasn't for a faster chip. It was for a faster proof. Yesterday, a consortium led by Shanghai-based BSN Labs and Horizen Asia quietly published a preprint detailing a custom ASIC design capable of generating Groth16 proofs at 120 proofs per second—3x the throughput of the current state-of-the-art FPGA solutions used by zkSync and Scroll. The accompanying GitHub repository shows a tape-out-ready layout fabricated on a 28nm process node, using lithography equipment that, according to anonymous sources, is entirely domestic Chinese steppers. This isn't a research paper. This is a declaration that the geographic monopoly on zero-knowledge computation hardware has just been broken.
Context
For the past three years, the narrative around ZK-rollups has been one of "centralization through hardware." Polygon, StarkWare, and even the Ethereum Foundation have publicly acknowledged that the most efficient prover networks depend on high-margin, low-volume chips manufactured by ASML’s EUV-lithography-dependent fabs in Taiwan and Korea. The assumption was simple: if you didn't have access to a 3nm TSMC wafer, you couldn't compete in the ZK-prover market. This created a natural moat for Western and Korean chip designers. But the calculus is shifting. China's semiconductor push, initially dismissed as a distant threat, has found its first crypto-native beachhead.
The breakthrough is not just a binary "China has ZK-ASIC." It's a systems-level achievement. The ASIC, codenamed "Jadeite-1," integrates a novel number-theoretic transform (NTT) engine optimized for the BLS12-381 curve, combined with a multi-threaded MSM (multi-scalar multiplication) accelerator. The critical detail: the entire design uses only standard cells and IP blocks that are available under open-source licenses or from domestic foundries like SMIC. This is not a clone of a Western design. It's a ground-up architecture tailored to the constraints of mature-node lithography—specifically, the 28nm DUV process that China’s Shanghai Micro Electronics Equipment (SMEE) can now produce at scale.
Core (Original Technical and Data Analysis)
Let's bypass the PR. The real story is in the supply chain decoupling. I spent the past 72 hours reverse-engineering the published performance benchmarks and cross-referencing them with foundry capacity data from IC Insights.
First, the throughput claim. 120 proofs per second is significant but not world-beating. For context, a single NVIDIA H100 GPU can achieve roughly 40 proofs per second using optimized CUDA kernels. The A100 does about 25. So 120 from a dedicated ASIC is a 3x improvement over the current GPU baseline—but still far behind the 1,000+ proofs per second promised by the next-gen ASICs from Cysic (currently on 5nm). However, the Jadeite-1's advantage isn't raw speed; it's cost per proof. Based on die size estimates (around 300mm² on 28nm), the unit cost could be as low as $150 in volume, compared to $30,000 for an H100. That's a 200x cost advantage.
Second, the lithography dependency. The preprint explicitly states that the chip was fabricated using "domestic 28nm immersion DUV tools." Let me validate that. SMEE’s SSA600/20, their latest 28nm scanner, has a theoretical overlay accuracy of 1.5nm and a throughput of 150 wafers per hour. That's similar to ASML's NXT:1980 from 2015. While not cutting-edge, it's more than sufficient for the 28nm node. The key bottleneck—lens assemblies—was until recently sourced from Carl Zeiss (Germany). However, a February 2026 report from the China Optics Society confirmed that Changchun Institute of Optics had developed a 0.33 numerical aperture objective lens system tailored for 28nm DUV. The collapse wasn't in the chip; the collapse was in the illusion that China couldn't do critical optical components.
Third, the ecosystem readiness. Horizen Asia confirmed in a Telegram AMA that they have already ported their ZK-EVM prover (a fork of Polygon's zkEVM) to the Jadeite-1 instruction set. Preliminary tests show a 70% reduction in proving time for ERC-20 transfers compared to CPU-based provers. More importantly, the ASIC includes a custom memory controller optimized for Merkle tree traversal, reducing memory bandwidth consumption by 40%. This is critical because memory bandwidth, not compute, is often the bottleneck in ZK-proof generation.
Contrarian Angle
The market will immediately frame this as "China winning the crypto hardware race." That's half-truth at best. The unreported angle is that this breakthrough actually confirms the deepening of a bifurcated ZK supply chain, not its unification. Jadeite-1 is stuck at 28nm. While 28nm is cheap and abundant, it is fundamentally limited for high-frequency proving in real-time applications. To reach the next milestone (500+ proofs per second), you need 7nm or better. SMEE does not have an EUV scanner. China's EUV development, according to leaked CAS documents, is still in the laboratory stage and at least 4 years from commercial viability.
Liquidity didn't drain from the market; it drained from the narrative. The real impact will be felt in the "low-end ZK" market: identity verification, off-chain gaming proofs, and decentralized sequencer networks where latency is not critical. Projects like =nil; (formerly =nil; Foundation) and StarkNet will face pricing pressure from Chinese prover networks offering 90% cheaper proofs. But for high-frequency trading applications like dYdX or perp DEXs, the low throughput means Jadeite-1 is not a viable replacement for centralized sequencers.
Sustainability is just a loan from the future. The Chinese consortium is taking a massive bet on 28nm volume. But if the market pivots to proof compression or recursive proofs (which reduce the number of total proofs needed), the ASIC's advantages could evaporate. Recursive proofs, pioneered by Zcash and now adopted by Mina, allow thousands of transactions to be verified with a single proof. That collapses the demand for raw prover throughput. Jadeite-1's architecture is not designed for recursive verification—it's optimized for single-proof generation. If recursive proof adoption explodes, this ASIC becomes obsolete within 18 months.
Trust is a variable, not a constant. The preprint is open-source, but the actual silicon fabrication is opaque. I've seen this pattern before: in 2019, Bitmain announced a Bitcoin ASIC fabricated on 7nm, only to later reveal it was actually 16nm with aggressive tweaks. The Jadeite-1 might be using an older 40nm process and repackaging it as 28nm—a common marketing tactic in Chinese fabs. Without independent die-shot analysis, the claims must be taken with a grain of salt.
Takeaway
The next watch isn't the proof-per-second benchmark. It's the Dutch government's response. ASML's lobbyists are already preparing a case to extend export controls to "dual-use lithography equipment capable of producing logic chips below 14nm." If that happens, Chinese fabs will be cut off from even the 28nm scanner upgrades needed to improve yield. The real race isn't between ZK-ASICs. The race is between Chinese DUV self-sufficiency and Western export control expansion. First in, first served, or first to flee.